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Introduction
This document contains some pointers to information on Formal Methods↑, useful for mathematically describing and reasoning about computer-based systems, available around the world on the World Wide Web (WWW). Formal methods are a fault avoidance technique that help in the reduction of errors introduced into a system, particularly at the earlier stages of design. They complement fault removal techniques like testing. Links for accessing online information in the following categories are available:
ACSR (Algebra of Communicating Shared Resources) and Graphical Communicating Shared Resources (GCSR), a formal language for the specification, refinement, and analysis of real-time systems. See the tools VERSA (Verification Execution and Rewrite System for ACSR) and PARAGON for visual specification and verification of real-time systems.
Action Semantics, a framework for specifying formal semantics of programming languages.
CADP: a widespread toolbox for the Construction and Analysis of Distributed Processes, developed at INRIA Grenoble
CASL: Common Algebraic Specification Language, for algebraic specification and development, from CoFI, the Common Framework Initiative.
CafeOBJ, an algebraic specification and programming language. A successor of OBJ.
CCS (Calculus of Communicating Systems). A process algebra for concurrent systems.
Circal (CIRcuit CALculus) System supporting a process algebra which may be used to rigorously describe, verify and simulate concurrent systems. See software.
Coq proof assistant: checks proofs about assertions, helps to find formal proofs and extracts certified programs from constructive proofs.
CSP (Communicating Sequential Processes) including the FDR2 (Failures-Divergence Refinement) tool.
CWBConcurrency Factory and CWB-NC (The Concurrency Workbench of North Carolina), which includes a LOTOS interface, diagnostic information, etc. Note: The CWB and CWB-NC have a common ancestor, but are each under separate development.
FormalCheck model checker tool for verifying the functionality of digital hardware designs in Verilog or VHDL, based on the COSPAN model checker.
HOL mechanical theorem proving system, based on Higher Order Logic.
HyTech (The HYbrid TECHnology Tool), an automatic tool for the analysis of embedded systems which computes the condition under which a linear hybrid system satisfies a temporal-logic requirement.
IMPS, an Interactive Mathematical Proof System intended to provide mechanical support for traditional mathematical techniques and styles of practice.
Isabelle, a generic theorem prover, supporting higher-order logic, ZF set theory, etc.
Jape (Just Another Proof Editor). A framework for building interactive proof editors.
JML (Java Modeling Language), a behavioral interface specification language for Java. See also ESC/Java2.
KeY An automatic and interactive, verification and test generation tool for Java Card.
KeYmaera A Hybrid Theorem Prover for Hybrid Systems.
KIV (Karlsruhe Interactive Verifier). A tool for the development of correct software using stepwise refinement.
Kronos, a verification tool for safety and liveness properties of real-time systems. Uses timed automata, TCTL (an extension of temporal logic) and model-checking.
Larch family of languages and tools supporting a two-tiered definitional style of specification. See especially LP, the Larch Prover.
LeanTAP, a tableau-based deduction theorem prover for classical first-order logic.
CSML and MCB, a language for compositional description of finite state machines and a (non-symbolic) model checker for CTL.
SMV (Symbolic Model Verifier) model checker for finite-state systems, using the specification language CTL (Computation Tree Logic), a propositional branching-time temporal logic. See also Word-level SMV for verifying arithmetic circuits efficiently. See also NuSMV, a new symbolic model checker.
Murphi description language and verifier tool for finite-state verification of concurrent systems.
Pobl. A development method for concurrent object-based programs.
ProofPower is a commercial tool, developed by ICL, supporting development and checking of specifications and formal proofs in Higher Order Logic and/or Z. Support for Z uses a deep(ish) embedding of Z into HOL, but includes syntax and type checking customized for Z.
Spec#, an extension of the C# programming language from Microsoft Research with specification features allowing static analysis using a program verifier.
Specware automated software development system for stepwise refinement of provably correct code. See also technology transfer information and publication from the Kestrel Institute.
SPIN is an automated verification tool (model checker), using PROMELA (PROcess MEta LAnguage), a language loosely based on CSP, for finite state systems, such as protocols or validation models of distributed systems, developed at Bell Laboratories. See also p2b, a translation utility.
StackAnalyzer, an abstract interpretation based static analyzer for computing the worst-case stack usage of tasks.
StateSim simulator for Statecharts models. Draw your models in Open Office Draw and the run your simulations from StateSim.
Statestep finite state machine modelling with comprehensive elicitation of unusual scenarios (addressing "corner cases" or the feature interaction problem).
TLA (Temporal Logic of Actions), a logic for specifying and reasoning about concurrent and reactive systems. See also Tools for TLA project.
TPS and ETPS, the Theorem Proving System and the Educational Theorem Proving System.
TRIO language and tools for real-time systems, based on temporal logic.
TTM/RTTL framework for real-time reactive systems.
UNITY, a programming notation and a logic to reason about parallel and distributed programs.
UPPAAL verification and validation tools for real-time systems. Model checking and simulation with a graphical interface.
VCC, Microsoft Research - Verification of Concurrent C; a sound deductive verifier for C.
VeriSoft, Bell Laboratories, Lucent Technologies. A model checking tool for systematic software testing of concurrent/reactive/real-time systems. Automatically searches for coordination problems (deadlocks, etc.) and assertion violations. Supports C, C++, etc.
VIS (Verification Interacting with Synthesis), a system for formal verification, synthesis, and simulation of finite state systems, especially logic circuits. Includes a Verilog HDL front-end.
There are a significant number of mailing lists concerning individual formal methods. Please see the relevant pages for the formal methods of interest for details.